With some current-server blades, storage capacity is limited. One architecture that can be used to increase the storage capacity of a system with such server blades involves installation of a storage blade in proximity to the server blade. The server blade and the storage blade communicate through an x4 PCI-Express (PCIe) link. However, the backplane used with the blades does not support a common reference clock. Furthermore, because the current x86 clock architecture implements a low cost crystal plus clock generator with multiple output frequencies, the clock source on servers as well as on server blade systems tends to have a large phase jitter. In addition, most chip vendors implement low cost digital CDR (clock-data-recovery) circuitry, which may not work properly in a high phase jitter environment.
Due to the separate reference clock (refclk) used on the current blade architecture, SSC (spread-spectrum-clocking) cannot be supported. Any such attempt to use spread spectrum clocking likely will make those architectures vulnerable to failure.